One technique to protect the components (e.g., transistors, inactive devices, etc) of an integrated circuit from an electrostatic discharge (ESD) event is to add circuitry intended to sink or remove the charge associated with the ESD event. For example, a wide clamping device (e.g. a transistor having a width significant to allow the charge to drain away without creating a damaging current density) may be placed in parallel or in series with the portion of the integrated circuit to be protected. Due to the width of the clamping device, it is typically able to sink the charge associated with the ESD device and alleviate high voltage levels that may otherwise result.
However, as manufacturing techniques improve, the channel length of transistors is typically reduced, which, in turn, may increase the sub-threshold leakage of the transistors. Consequently, the clamping devices may become a significant source of leakage current while the integrated circuit is in operation. Thus, there is a continuing need for better ways to provide charge protection to an integrated circuit that have reduced leakage currents.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.